A Reconfigurable Computing In-Memory Macro with Charge-sharing-based Weighted Accumulator
This work offers significant improvements in efficiency and performance for researchers and engineers developing analog computing-in-memory systems, particularly in reducing ADC overhead and latency.
This paper addresses challenges in SRAM-based analog computing-in-memory by proposing a reconfigurable 256x128 array. It achieves a 9x improvement in IMADC area overhead, reduces latency by up to 6.6x, and improves read bitline voltage by 3.5x.
SRAM-based analog computing-in-memory demonstrates outstanding efficiency. However, it faces three critical challenges: significant ADC overhead, high latency for multi-bit inputs, and limited read bitline voltage. To address these issues, this work proposes a multi-bit highly reconfigurable 256x128 in-memory computing array supporting 1-7b input, 2-4b weight, and 1-7b output. Three key innovations are introduced: 1) The IMADC occupies only 3% area overhead, achieving a 9x improvement compared to previous IMADC; 2) The BSCHA reduces latency by 1.9x and 6.6x compared to traditional pulse-width modulation (PWM) and bit-slicing modes, respectively; 3) A dual-8T bitcell enabling ternary weight storage through a decoupled read path, integrated with a read wordline under-driven cascode technique, improves linearity of unit discharge current by 7x and increases the usable read bitline voltage by 3.5x.