Accelerating NBTI Aging Evaluation via Physics-Aware Graph Attention Networks
This work provides a significantly faster and accurate method for evaluating semiconductor device aging, which is crucial for engineers and designers working on reliability in advanced process nodes.
This paper addresses the computational bottleneck of evaluating Negative Bias Temperature Instability (NBTI) aging in semiconductor devices, which is critical for reliability-aware Design-Technology Co-Optimization (DTCO). They developed a physics-aware graph attention network (Physics-Aware RelGAT) that predicts device degradation characteristics with a mean error of 1.27% on an independent test set, achieving a 17,000x acceleration over traditional TCAD simulations.
As semiconductor technology advances to smaller nodes, Negative Bias Temperature Instability (NBTI) under prolonged workloads has emerged as a significant bottleneck constraining reliability-aware Design-Technology Co-Optimization (DTCO). Conventional TCAD simulations incur prohibitive computational overhead when evaluating device aging characteristics, making it difficult to satisfy the demand for efficient iterative design cycles. To address this challenge, this paper proposes an aging evaluation framework based on a physics-aware graph attention network (Physics-Aware RelGAT). By losslessly mapping unstructured device meshes into attributed graphs, this framework constructs a 45-dimensional device encoding scheme that integrates interface trap distributions and macroscopic electro-thermal stresses, achieving a direct mapping from underlying physical quantities to device degradation characteristics. To overcome the challenge of predicting currents that span multiple orders of magnitude, a dual-end normalization strategy and a log-scale loss function optimization are introduced, ensuring the model possesses high-precision fitting capabilities. Experimental results demonstrate that the model achieves a mean error of only 1.27% on an independent test set, achieving an acceleration of approximately 17,000 times compared to traditional TCAD simulations. This framework provides a solution for the assessment of circuit reliability in advanced process nodes that successfully balances physical fidelity with industrial-grade efficiency.