BigPower: Hierarchical Source-Level Module Power Estimation for CPUs with Large Language Models
For CPU designers, BigPower offers a practical alternative to simulation-based power estimation, though it is domain-specific and incremental.
BigPower introduces a hierarchical source-level model using LLMs to estimate CPU module power directly from design information, achieving fine-grained estimation without simulation. On the XiangShan processor, it provides efficient power estimation across configurations and workloads.
Accurate power estimation is important for understanding and optimizing CPU power behavior, yet practical workflows often rely on simulation-derived information or post-silicon analysis. In this work, we present BigPower, a hierarchical source-level surrogate model for fine-grained module-level power estimation during CPU design. BigPower leverages large language model-based representations together with architectural hierarchy, module connectivity, configuration parameters, and workload context to estimate module-level power consumption directly from source-level design information, without requiring additional simulation during inference. Experimental results in the open-source XiangShan processor family demonstrate practical fine-grained power estimation across diverse configurations and workloads, offering an efficient alternative to conventional simulation-based workflows.