Information Flow Paths from RTL Traces
For hardware validation engineers, this work automates the generation of information flow paths, reducing manual effort and potential errors in security property validation.
The paper addresses the challenge of automated security validation in hardware design by developing a novel approach to construct information flow paths from RTL trace data, enabling full path reproduction of sensitive information propagation. The method improves upon prior work that was limited to detecting flows between registers without path details.
Security validation is an important yet challenging part of the hardware design process, yet, by convention, validation engineers are tasked with defining the threat model, specifying the relevant security properties, detecting any violations of those properties, and assessing the consequences to system security, each of which is manually intensive and may introduce errors. The combined technologies of information flow tracking and specification mining represent an automated approach to property generation and validation, but prior work on information flow tracking on RTL trace data was limited to find cases under which information flowed between registers, without reproducing full paths to capture how sensitive information propagates through a design. With the introduction of new technologies accelerating hardware analysis, we develop a novel approach for constructing information flow paths from register transfer level (RTL) trace data.