A3C3: AI Algorithm and Accelerator Co-design, Co-search, and Co-generation
This work addresses the inefficiency of decoupled algorithm and hardware design for AI system developers, but as a book chapter it is an incremental overview rather than a novel contribution.
A3C3 proposes a holistic co-design, co-search, and co-generation methodology for AI algorithms and accelerators, jointly optimizing neural network architectures and hardware implementations to improve accuracy, latency, throughput, energy efficiency, and hardware utilization over traditional separate design flows.
We present a holistic methodology for artificial intelligence algorithm and accelerator co-design, co-search, and co-generation (A3C3), which jointly optimizes neural network architectures and their hardware implementations to address the inefficiencies of traditional top-down AI system design flows. Conventional AI deployment often treats model design and hardware mapping as separate stages: an algorithm is first developed for accuracy, and only afterward adapted to meet latency, throughput, energy, or resource constraints. This separation can lead to suboptimal systems, particularly as modern AI workloads become increasingly heterogeneous, memory-intensive, and platform-dependent. A3C3 instead parameterizes both algorithmic and accelerator design spaces and searches them jointly, enabling the automatic generation of model-accelerator pairs that better balance accuracy, latency, throughput, energy efficiency, and hardware utilization. This article is a book chapter of the Handbook of Embedded Machine Learning, edited by Sudeep Pasricha and Muhammad Shafique, Springer Nature.