CSCO: A Backside-PDN-Aware Clock-Signal Co-Optimization Framework for Improved PPA
For chip designers using advanced BSPDN technology, CSCO addresses the critical tradeoff of backside resource allocation between clock and signal nets, improving PPA and SI robustness.
CSCO is a framework that jointly allocates limited backside routing resources between clock and signal nets in backside power delivery networks (BSPDN), improving worst-negative slack (WNS), total-negative slack (TNS), frequency, and signal integrity without additional shielding overhead.
Backside power delivery networks (BSPDN) have emerged as a promising technology for advanced logic nodes to address IR-drop and PPA challenges. While BSPDN introduces additional routing resources on the backside, these resources are limited and must be carefully partitioned between clock and signal nets, creating a critical resource allocation tradeoff. Prior work either moves only the clock network or assumes a fixed clock tree and optimizes only signal nets, failing to explore the tradeoff space of backside resource allocation. Moreover, lacking frontside power-ground shielding, BSPDN introduces severe signal integrity (SI) degradation. We propose CSCO, a data-driven BSPDN-aware co-optimization framework that jointly allocates limited backside resources between clock and signal nets across frontside/backside layers. CSCO employs efficient search strategies to identify critical nets for backside routing without repeated evaluation, navigating the clock-signal allocation tradeoff to balance IR-drop, routing congestion, and PPA. The framework also leverages backside routing to mitigate coupling noise and crosstalk-induced SI issues. Experiments demonstrate improved WNS/TNS, frequency, and SI robustness without additional shielding overhead.