Ed Younis

Mathias Weiden, Ed Younis, Justin Kalloor et al.

In the Noisy Intermediate Scale Quantum (NISQ) era, finding implementations of quantum algorithms that minimize the number of expensive and error prone multi-qubit gates is vital to ensure computations produce meaningful outputs. Unitary synthesis, the process of finding a quantum circuit that implements some target unitary matrix, is able to solve this problem optimally in many cases. However, current bottom-up unitary synthesis algorithms are limited by their exponentially growing run times. We show how applying machine learning to unitary datasets permits drastic speedups for synthesis algorithms. This paper presents QSeed, a seeded synthesis algorithm that employs a learned model to quickly propose resource efficient circuit implementations of unitaries. QSeed maintains low gate counts and offers a speedup of $3.7\times$ in synthesis time over the state of the art for a 64 qubit modular exponentiation circuit, a core component in Shor's factoring algorithm. QSeed's performance improvements also generalize to families of circuits not seen during the training process.

Bao Bach, Ilya Safro, Ed Younis

With the growth of quantum platforms for gate-based quantum computation, compilation holds a crucial role in deciding the success of the implementation. While there has been rich research in compilation techniques for the superconducting-qubit regime. The trapped-ion architectures, currently leading in robust quantum computations for their reliable operations, still lack competitive compilation strategies. This work introduces a unifying hardware abstraction, the ``position graph'', representing various hardware architectures. With this abstraction, we model trapped-ion Quantum Charge-Coupled Device (QCCD) architectures, enabling high-quality, scalable compilation methods. Specifically, we propose scheduling algorithms called SHuttling-Aware PERmutative (SHAPER) and SHuttling-AWare (SHAW) heuristic searches to tackle the complex constraints and dynamics of trapped-ion machines, with the cooperation of state-of-the-art permutation-aware mapping. These approaches generate executable circuits and native instructions that respect the physical constraints of shuttling-based architectures. We evaluate proposed algorithms across theorized and real architectures using the position graph framework. For completeness, we also introduce a linear program of trapped-ion scheduling that yields the optimal schedules, enabling a direct comparison with our heuristics. Our algorithm can successfully compile programs for extreme architectures where priori algorithms fail. When the baseline does complete, our produced schedules are $1.45$ times faster on average, with best-case speedups up to $4$ times faster.