Chenyun Pan

Qianhou Qu, Sheng Lu, Sungyong Jung et al.

Spiking neural networks (SNNs) provide an efficient event-driven computing paradigm for bio-inspired interception tasks. However, most implementations rely on von Neumann digital computing platforms, where memory and computation bottlenecks limit energy efficiency. This work presents a compact and energy-efficient memristive neuromorphic accelerator for bio-inspired interception tasks. A novel one-transistor-one-resistor (1T1R) crossbar array is designed to emulate synaptic operations in the in-memory computing (IMC) domain, while circuit-level optimization mitigates membrane drift and improves integration fidelity. In addition, an integrate-and-fire (IF) neuron with separated input and membrane nodes is developed to improve inference robustness during array-interfaced operation. Implemented in the SkyWater SKY130 PDK, the proposed neuron achieves an energy consumption of 10.67 pJ/spike and an area of 906 um^2. System-level results show that the memristive IMC output closely matches the software SNN baseline, with a correlation coefficient of 0.9622, while achieving a 96% interception success rate. These results demonstrate the effectiveness of the proposed design for compact and reliable memristive SNN inference in bio-inspired interception tasks.

Qianhou Qu, Sheng Lu, Liuting Shang et al.

Spiking neural networks (SNNs) provide event-driven and low-power computation inspired by biological neural systems, but current implementations rely on von Neumann graphics processing units (GPUs) and central processing units (CPUs) platforms, where memory and computation bottlenecks limit energy efficiency. To address this challenge, this paper proposes an analog memristor-based spiking neural network (SNN) accelerator that integrates in-memory synaptic computation with analog integrate-and-fire (IF) neurons, eliminating multi-transistor CMOS synapse circuits and enabling asynchronous event-driven operation at the 45nm technology node. Additionally, a digital SNN accelerator is designed and optimized at the 5 nm technology node for comparison. The proposed architecture is evaluated using a predator-prey tracking task that emulates pursuit behavior. In this task, the analog SNN accelerator's inference closely matches the ideal software inference with a mean squared error (MSE) of 0.004. HSPICE simulation results show that the proposed analog SNN accelerator achieves 12.7 times lower energy consumption and 1.26 times lower delay compared to the digital baseline, demonstrating the potential of memristor-based neuromorphic circuits for energy-efficient real-time edge intelligence.

Qiuwen Lou, Chenyun Pan, John McGuiness et al.

Deep neural network (DNN) accelerators with improved energy and delay are desirable for meeting the requirements of hardware targeted for IoT and edge computing systems. Convolutional neural networks (CoNNs) belong to one of the most popular types of DNN architectures. This paper presents the design and evaluation of an accelerator for CoNNs. The system-level architecture is based on mixed-signal, cellular neural networks (CeNNs). Specifically, we present (i) the implementation of different layers, including convolution, ReLU, and pooling, in a CoNN using CeNN, (ii) modified CoNN structures with CeNN-friendly layers to reduce computational overheads typically associated with a CoNN, (iii) a mixed-signal CeNN architecture that performs CoNN computations in the analog and mixed signal domain, and (iv) design space exploration that identifies what CeNN-based algorithm and architectural features fare best compared to existing algorithms and architectures when evaluated over common datasets -- MNIST and CIFAR-10. Notably, the proposed approach can lead to 8.7$\times$ improvements in energy-delay product (EDP) per digit classification for the MNIST dataset at iso-accuracy when compared with the state-of-the-art DNN engine, while our approach could offer 4.3$\times$ improvements in EDP when compared to other network implementations for the CIFAR-10 dataset.