Dietmar Fey

Vlad Cnejevici, Matthias Ponfick, Dietmar Fey et al.

Loss of voluntary foot movement after spinal cord injury (SCI) can significantly limit independent mobility and quality of life. To improve motor output after injury, functional electrical stimulation (FES) is used to deliver stimulation pulses through the skin to affected muscles. While commercial FES systems typically use motion-based triggers, prior research shows that spared movement intent can be decoded after SCI using surface electromyography (EMG). Our aim is to assess how well spared neural signals of the lower limb after SCI can be decoded and used to control electrical stimulation for restoring foot movement. We developed a wearable machine learning-powered neuroprosthetic that records EMG from the affected lower limb using a 32-channel electrode bracelet and enables closed-loop control of a FES device for foot movement restoration. Five participants with SCI used the predicted control signal to follow trajectories on a screen with their foot and achieve distinct motor activation patterns for foot flexion, extension, and inversion or eversion. Three of these participants also achieved 2 proportional activation levels during foot flexion/extension with more than 70% accuracy. To validate how these neural signals can be used for closed-loop neuroprosthetic control, two participants used their decoded activity to control a FES device and stimulate their affected foot. This resulted in an increased foot flexion range for both participants of 33.6% and 40% of a functional healthy range, respectively (p smaller than 0.001). One of the participants also achieved voluntary proportional control of up to 6 stimulation levels during foot flexion/extension. These results suggest that wearable EMG decoding coupled with FES systems provides a scalable strategy for closed-loop neuroprosthetic control supporting voluntary foot movement.

Franz Richter-Gottfried, Alexander Ditter, Dietmar Fey

Designing hardware is a time-consuming and complex process. Realization of both, embedded and high-performance applications can benefit from a design process on a higher level of abstraction. This helps to reduce development time and allows to iteratively test and optimize the hardware design during development, as common in software development. We present our tool, OCLAcc, which allows the generation of entire FPGA-based hardware accelerators from OpenCL and discuss the major novelties of OpenCL 2.0 and how they can be realized in hardware using OCLAcc.

Christian Hartmann, Anna Yupatova, Marc Reichenbach et al.

Image processing applications are common in every field of our daily life. However, most of them are very complex and contain several tasks with different complexities which result in varying requirements for computing architectures. Nevertheless, a general processing scheme in every image processing application has a similar structure, called image processing pipeline: (1) capturing an image, (2) pre-processing using local operators, (3) processing with global operators and (4) post-processing using complex operations. Therefore, application-specialized hardware solutions based on heterogeneous architectures are used for image processing. Unfortunately the development of applications for heterogeneous hardware architectures is challenging due to the distribution of computational tasks among processors and programmable logic units. Nowadays, image processing systems are started from scratch which is time-consuming, error-prone and inflexible. A new methodology for modeling and implementing is needed in order to reduce the development time of heterogenous image processing systems. This paper introduces a new holistic top down approach for image processing systems. Two challenges have to be investigated. First, designers ought to be able to model their complete image processing pipeline on an abstract layer using UML. Second, we want to close the gap between the abstract system and the system architecture.

Oliver Reiche, Konrad Häublein, Marc Reichenbach et al.

In the domain of image processing, often real-time constraints are required. In particular, in safety-critical applications, such as X-ray computed tomography in medical imaging or advanced driver assistance systems in the automotive domain, timing is of utmost importance. A common approach to maintain real-time capabilities of compute-intensive applications is to offload those computations to dedicated accelerator hardware, such as Field Programmable Gate Arrays (FPGAs). Programming such architectures is a challenging task, with respect to the typical FPGA-specific design criteria: Achievable overall algorithm latency and resource usage of FPGA primitives (BRAM, FF, LUT, and DSP). High-Level Synthesis (HLS) dramatically simplifies this task by enabling the description of algorithms in well-known higher languages (C/C++) and its automatic synthesis that can be accomplished by HLS tools. However, algorithm developers still need expert knowledge about the target architecture, in order to achieve satisfying results. Therefore, in previous work, we have shown that elevating the description of image algorithms to an even higher abstraction level, by using a Domain-Specific Language (DSL), can significantly cut down the complexity for designing such algorithms for FPGAs. To give the developer even more control over the common trade-off, latency vs. resource usage, we will present an automatic optimization process where these criteria are analyzed and fed back to the DSL compiler, in order to generate code that is closer to the desired design specifications. Finally, we generate code for stereo block matching algorithms and compare it with handwritten implementations to quantify the quality of our results.

Frank Hannig, Dietmar Fey, Anton Lokhmotov

This volume contains the papers accepted at the DATE Friday Workshop on Heterogeneous Architectures and Design Methods for Embedded Image Systems (HIS 2015), held in Grenoble, France, March 13, 2015. HIS 2015 was co-located with the Conference on Design, Automation and Test in Europe (DATE).