Chaotic multi-objective optimization based design of fractional order PIλDμ controller in AVR system
This addresses controller design for AVR systems, but it appears incremental as it builds on existing methods with minor enhancements.
The paper tackled the design of a fractional order PIλDμ controller for an Automatic Voltage Regulator (AVR) system by using an improved chaotic NSGA II algorithm for multi-objective optimization, resulting in Pareto fronts that show trade-offs and a comparative analysis with standard PID controllers.
In this paper, a fractional order (FO) PIλDμcontroller is designed to take care of various contradictory objective functions for an Automatic Voltage Regulator (AVR) system. An improved evolutionary Non-dominated Sorting Genetic Algorithm II (NSGA II), which is augmented with a chaotic map for greater effectiveness, is used for the multi-objective optimization problem. The Pareto fronts showing the trade-off between different design criteria are obtained for the PIλDμand PID controller. A comparative analysis is done with respect to the standard PID controller to demonstrate the merits and demerits of the fractional order PIλDμcontroller.