Simple SIMON: FPGA implementations of the SIMON 64/128 Block Cipher
This work addresses hardware implementation challenges for a specific cryptographic cipher, which is incremental as it applies existing methods to new hardware designs.
The paper tackled implementing the SIMON 64/128 block cipher on FPGA hardware, presenting various architectures with encryption, decryption, and key-scheduling capabilities, and reported performance results on Xilinx Spartan-6 FPGAs.
In this paper we will present various hardware architecture designs for implementing the SIMON 64/128 block cipher as a cryptographic component offering encryption, decryption and self-contained key-scheduling capabilities and discuss the issues and design options we encountered and the tradeoffs we made in implementing them. Finally, we will present the results of our hardware architectures' implementation performances on the Xilinx Spartan-6 FPGA series.