A compact aVLSI conductance-based silicon neuron
This work provides a domain-specific solution for neuromorphic computing by enabling high-density integration of silicon neurons, though it is incremental as it builds on existing aVLSI and conductance-based neuron designs.
The authors tackled the problem of implementing a compact, high-speed conductance-based silicon neuron for neuromorphic systems by designing an aVLSI circuit with digital control, resulting in a neuron area of ~26.5 um² capable of emulating various biological spiking behaviors.
We present an analogue Very Large Scale Integration (aVLSI) implementation that uses first-order lowpass filters to implement a conductance-based silicon neuron for high-speed neuromorphic systems. The aVLSI neuron consists of a soma (cell body) and a single synapse, which is capable of linearly summing both the excitatory and inhibitory postsynaptic potentials (EPSP and IPSP) generated by the spikes arriving from different sources. Rather than biasing the silicon neuron with different parameters for different spiking patterns, as is typically done, we provide digital control signals, generated by an FPGA, to the silicon neuron to obtain different spiking behaviours. The proposed neuron is only ~26.5 um2 in the IBM 130nm process and thus can be integrated at very high density. Circuit simulations show that this neuron can emulate different spiking behaviours observed in biological neurons.