FPGA Implementation of $\mathbb{F}_2$-Linear Pseudorandom Number Generators Based on Zynq MPSoC: a Chaotic Iterations Post Processing Case Study
This work addresses hardware security needs by optimizing PRNG implementations for FPGA platforms, though it is incremental as it builds on existing PRNG families and methods.
The authors implemented and compared 18 pseudorandom number generators (PRNGs) on an FPGA, analyzing their area, throughput, and statistical performance, and found that using chaotic iterations as post-processing improved the statistical profile of a combined PRNG that previously failed TestU01 tests.
Pseudorandom number generation (PRNG) is a key element in hardware security platforms like field-programmable gate array FPGA circuits. In this article, 18 PRNGs belonging in 4 families (xorshift, LFSR, TGFSR, and LCG) are physically implemented in a FPGA and compared in terms of area, throughput, and statistical tests. Two flows of conception are used for Register Transfer Level (RTL) and High-level Synthesis (HLS). Additionally, the relations between linear complexity, seeds, and arithmetic operations on the one hand, and the resources deployed in FPGA on the other hand, are deeply investigated. In order to do that, a SoC based on Zynq EPP with ARM Cortex-$A9$ MPSoC is developed to accelerate the implementation and the tests of various PRNGs on FPGA hardware. A case study is finally proposed using chaotic iterations as a post processing for FPGA. The latter has improved the statistical profile of a combination of PRNGs that, without it, failed in the so-called TestU01 statistical battery of tests.