Hardware design of LIF with Latency neuron model with memristive STDP synapses
This work addresses hardware design for neuromorphic computing, but it is incremental as it builds on existing neuron and synapse models with a specific circuit implementation.
The authors tackled the hardware implementation of a neuromorphic system using a Leaky Integrate-and-Fire with Latency (LIFL) neuron and memristive STDP synapses, achieving validation through simulation of a three-neuron, two-synapse motif.
In this paper, the hardware implementation of a neuromorphic system is presented. This system is composed of a Leaky Integrate-and-Fire with Latency (LIFL) neuron and a Spike-Timing Dependent Plasticity (STDP) synapse. LIFL neuron model allows to encode more information than the common Integrate-and-Fire models, typically considered for neuromorphic implementations. In our system LIFL neuron is implemented using CMOS circuits while memristor is used for the implementation of the STDP synapse. A description of the entire circuit is provided. Finally, the capabilities of the proposed architecture have been evaluated by simulating a motif composed of three neurons and two synapses. The simulation results confirm the validity of the proposed system and its suitability for the design of more complex spiking neural networks