PCNN: Pattern-based Fine-Grained Regular Pruning towards Optimizing CNN Accelerators
This work addresses the challenge of deploying CNNs on resource-constrained hardware accelerators by providing a compression method that balances accuracy and efficiency, though it is incremental as it builds on existing pruning techniques.
The paper tackles the problem of compressing convolutional neural networks (CNNs) for efficient hardware acceleration by proposing PCNN, a fine-grained regular pruning method, which achieves up to 8.4x compression with only 0.2% accuracy loss on models like VGG-16 and ResNet-18, and demonstrates hardware implementation with up to 9.0x speedup and high energy efficiency.
Weight pruning is a powerful technique to realize model compression. We propose PCNN, a fine-grained regular 1D pruning method. A novel index format called Sparsity Pattern Mask (SPM) is presented to encode the sparsity in PCNN. Leveraging SPM with limited pruning patterns and non-zero sequences with equal length, PCNN can be efficiently employed in hardware. Evaluated on VGG-16 and ResNet-18, our PCNN achieves the compression rate up to 8.4X with only 0.2% accuracy loss. We also implement a pattern-aware architecture in 55nm process, achieving up to 9.0X speedup and 28.39 TOPS/W efficiency with only 3.1% on-chip memory overhead of indices.