Bit Error Robustness for Energy-Efficient DNN Accelerators
This addresses energy efficiency for DNN accelerators, offering incremental improvements in robustness and trade-offs for practical deployment.
The paper tackles the problem of bit errors in low-voltage DNN accelerators, which reduce energy consumption but cause failures in weight memory, and shows that combining robust quantization, weight clipping, and random bit error training improves robustness, enabling energy savings of 20% with less than 1% accuracy loss on CIFAR-10.
Deep neural network (DNN) accelerators received considerable attention in past years due to saved energy compared to mainstream hardware. Low-voltage operation of DNN accelerators allows to further reduce energy consumption significantly, however, causes bit-level failures in the memory storing the quantized DNN weights. In this paper, we show that a combination of robust fixed-point quantization, weight clipping, and random bit error training (RandBET) improves robustness against random bit errors in (quantized) DNN weights significantly. This leads to high energy savings from both low-voltage operation as well as low-precision quantization. Our approach generalizes across operating voltages and accelerators, as demonstrated on bit errors from profiled SRAM arrays. We also discuss why weight clipping alone is already a quite effective way to achieve robustness against bit errors. Moreover, we specifically discuss the involved trade-offs regarding accuracy, robustness and precision: Without losing more than 1% in accuracy compared to a normally trained 8-bit DNN, we can reduce energy consumption on CIFAR-10 by 20%. Higher energy savings of, e.g., 30%, are possible at the cost of 2.5% accuracy, even for 4-bit DNNs.