Fast Arithmetic Hardware Library For RLWE-Based Homomorphic Encryption
This work addresses performance bottlenecks for users of homomorphic encryption in secure cloud computing, though it is incremental as it builds on existing hardware acceleration methods.
The authors tackled the problem of slow arithmetic operations in RLWE-based homomorphic encryption by designing an open-source hardware library, resulting in speedups of approximately 4200x for multiplication and 2950x for addition compared to software.
In this work, we propose an open-source, first-of-its-kind, arithmetic hardware library with a focus on accelerating the arithmetic operations involved in Ring Learning with Error (RLWE)-based somewhat homomorphic encryption (SHE). We design and implement a hardware accelerator consisting of submodules like Residue Number System (RNS), Chinese Remainder Theorem (CRT), NTT-based polynomial multiplication, modulo inverse, modulo reduction, and all the other polynomial and scalar operations involved in SHE. For all of these operations, wherever possible, we include a hardware-cost efficient serial and a fast parallel implementation in the library. A modular and parameterized design approach helps in easy customization and also provides flexibility to extend these operations for use in most homomorphic encryption applications that fit well into emerging FPGA-equipped cloud architectures. Using the submodules from the library, we prototype a hardware accelerator on FPGA. The evaluation of this hardware accelerator shows a speed up of approximately 4200x and 2950x to evaluate a homomorphic multiplication and addition respectively when compared to an existing software implementation.