SpinAPS: A High-Performance Spintronic Accelerator for Probabilistic Spiking Neural Networks
This work addresses the need for efficient hardware accelerators for SNNs, particularly in edge computing applications, though it is incremental as it builds on existing spintronic and SNN methods.
The authors tackled the problem of accelerating probabilistic spiking neural networks (SNNs) by proposing SpinAPS, a hardware accelerator using spintronic devices, which achieved a 4x performance improvement in energy efficiency and comparable accuracy to equivalent ANNs on benchmarks like handwritten digit recognition.
We discuss a high-performance and high-throughput hardware accelerator for probabilistic Spiking Neural Networks (SNNs) based on Generalized Linear Model (GLM) neurons, that uses binary STT-RAM devices as synapses and digital CMOS logic for neurons. The inference accelerator, termed "SpinAPS" for Spintronic Accelerator for Probabilistic SNNs, implements a principled direct learning rule for first-to-spike decoding without the need for conversion from pre-trained ANNs. The proposed solution is shown to achieve comparable performance with an equivalent ANN on handwritten digit and human activity recognition benchmarks. The inference engine, SpinAPS, is shown through software emulation tools to achieve 4x performance improvement in terms of GSOPS/W/mm2 when compared to an equivalent SRAM-based design. The architecture leverages probabilistic spiking neural networks that employ first-to-spike decoding rule to make inference decisions at low latencies, achieving 75% of the test performance in as few as 4 algorithmic time steps on the handwritten digit benchmark. The accelerator also exhibits competitive performance with other memristor-based DNN/SNN accelerators and state-of-the-art GPUs.