OpeNPDN: A Neural-network-based Framework for Power Delivery Network Synthesis
This work addresses power delivery network synthesis for chip design, offering a domain-specific improvement that is incremental in nature.
The paper tackles the time-intensive task of power delivery network (PDN) design by proposing a neural-network-based framework that uses convolutional neural networks to select PDN templates, incrementally refining grids from floorplan to placement stages. On average, it frees thousands of routing tracks in congestion-critical regions compared to a uniform PDN while meeting IR drop and electromigration specifications.
Power delivery network (PDN) design is a nontrivial, time-intensive, and iterative task. Correct PDN design must account for considerations related to power bumps, currents, blockages, and signal congestion distribution patterns. This work proposes a machine learning-based methodology that employs a set of predefined PDN templates. At the floorplan stage, coarse estimates of current, congestion, macro/blockages, and C4 bump distributions are used to synthesize a grid for early design. At the placement stage, the grid is incrementally refined based on more accurate and fine-grained distributions of current and congestion. At each stage, a convolutional neural network (CNN) selects an appropriate PDN template for each region on the chip, building a safe-by-construction PDN that meets IR drop and electromigration (EM) specifications. The CNN is initially trained using a large synthetically-created dataset, following which transfer learning is leveraged to bridge the gap between real-circuit data (with a limited dataset size) and synthetically-generated data. On average, the optimization of the PDN frees thousands of routing tracks in congestion-critical regions, when compared to a globally uniform PDN, while staying within the IR drop and EM limits.