A Deep-Learning-Aided Pipeline for Efficient Post-Silicon Tuning
This addresses the challenge of manual tuning for complex chips, which is incremental as it applies existing deep learning methods to a specific domain problem.
The paper tackled the problem of inefficient post-silicon tuning in chip validation by leveraging neural networks to select relevant variables, resulting in a deep-learning-aided pipeline that improves efficiency.
In post-silicon validation, tuning is to find the values for the tuning knobs, potentially as a function of process parameters and/or known operating conditions. In this sense, an more efficient tuning requires identifying the most critical tuning knobs and process parameters in terms of a given figure-of-merit for a Device Under Test (DUT). This is often manually conducted by experienced experts. However, with increasingly complex chips, manual inspection on a large amount of raw variables has become more challenging. In this work, we leverage neural networks to efficiently select the most relevant variables and present a corresponding deep-learning-aided pipeline for efficient tuning.