An Open-Source ML-Based Full-Stack Optimization Framework for Machine Learning Accelerators
This work addresses the need for efficient optimization in hardware design for ML accelerators, representing an incremental improvement by integrating existing techniques into a unified framework.
The authors tackled the problem of design space exploration for machine learning accelerators by proposing a physical-design-driven, learning-based prediction framework that combines backend PPA analysis with frontend simulation, achieving an average prediction error of 7% or less for ASIC implementations in 12 nm and 45 nm processes.
Parameterizable machine learning (ML) accelerators are the product of recent breakthroughs in ML. To fully enable their design space exploration (DSE), we propose a physical-design-driven, learning-based prediction framework for hardware-accelerated deep neural network (DNN) and non-DNN ML algorithms. It adopts a unified approach that combines backend power, performance, and area (PPA) analysis with frontend performance simulation, thereby achieving a realistic estimation of both backend PPA and system metrics such as runtime and energy. In addition, our framework includes a fully automated DSE technique, which optimizes backend and system metrics through an automated search of architectural and backend parameters. Experimental studies show that our approach consistently predicts backend PPA and system metrics with an average 7% or less prediction error for the ASIC implementation of two deep learning accelerator platforms, VTA and VeriGOOD-ML, in both a commercial 12 nm process and a research-oriented 45 nm process.