PANDA: Architecture-Level Power Evaluation by Unifying Analytical and Machine Learning Solutions
This addresses a critical bottleneck in microprocessor design for engineers, enabling efficient evaluation of architectural decisions under realistic data constraints, though it is an incremental improvement over prior hybrid methods.
The paper tackles the challenge of accurately modeling microprocessor power at the architectural level, where existing analytical models are unreliable and machine learning methods fail with limited training data. It proposes PANDA, a unified solution combining analytical and ML approaches, achieving high accuracy on new designs with minimal training and extending predictions to area, performance, energy, and new technology nodes.
Power efficiency is a critical design objective in modern microprocessor design. To evaluate the impact of architectural-level design decisions, an accurate yet efficient architecture-level power model is desired. However, widely adopted data-independent analytical power models like McPAT and Wattch have been criticized for their unreliable accuracy. While some machine learning (ML) methods have been proposed for architecture-level power modeling, they rely on sufficient known designs for training and perform poorly when the number of available designs is limited, which is typically the case in realistic scenarios. In this work, we derive a general formulation that unifies existing architecture-level power models. Based on the formulation, we propose PANDA, an innovative architecture-level solution that combines the advantages of analytical and ML power models. It achieves unprecedented high accuracy on unknown new designs even when there are very limited designs for training, which is a common challenge in practice. Besides being an excellent power model, it can predict area, performance, and energy accurately. PANDA further supports power prediction for unknown new technology nodes. In our experiments, besides validating the superior performance and the wide range of functionalities of PANDA, we also propose an application scenario, where PANDA proves to identify high-performance design configurations given a power constraint.