EDA-Aware RTL Generation with Large Language Models
This work addresses the challenge of reducing manual debugging in LLM-driven RTL code generation for hardware design, offering an incremental improvement through automated correction mechanisms.
The paper tackles the problem of generating error-free RTL code with large language models by introducing AIvril2, a self-verifying framework that uses multi-agent feedback from EDA tools to correct syntax and functional errors, achieving a 3.4× improvement in code quality and functional pass rates up to 77% for Verilog and 66% for VHDL.
Large Language Models (LLMs) have become increasingly popular for generating RTL code. However, producing error-free RTL code in a zero-shot setting remains highly challenging for even state-of-the-art LLMs, often leading to issues that require manual, iterative refinement. This additional debugging process can dramatically increase the verification workload, underscoring the need for robust, automated correction mechanisms to ensure code correctness from the start. In this work, we introduce AIvril2, a self-verifying, LLM-agnostic agentic framework aimed at enhancing RTL code generation through iterative corrections of both syntax and functional errors. Our approach leverages a collaborative multi-agent system that incorporates feedback from error logs generated by EDA tools to automatically identify and resolve design flaws. Experimental results, conducted on the VerilogEval-Human benchmark suite, demonstrate that our framework significantly improves code quality, achieving nearly a 3.4$\times$ enhancement over prior methods. In the best-case scenario, functional pass rates of 77% for Verilog and 66% for VHDL were obtained, thus substantially improving the reliability of LLM-driven RTL code generation.