Lorecast: Layout-Aware Performance and Power Forecasting from Natural Language
This addresses the labor-intensive and time-consuming nature of traditional chip design forecasting methods, offering a fast and user-friendly alternative for chip designers.
The paper tackles the problem of obtaining reliable performance and power forecasts in chip design planning by introducing Lorecast, a method that uses English prompts to generate layout-aware estimates, achieving accuracy within a few percent of error compared to post-layout analysis and significantly reducing turnaround time.
In chip design planning, obtaining reliable performance and power forecasts for various design options is of critical importance. Traditionally, this involves using system-level models, which often lack accuracy, or trial synthesis, which is both labor-intensive and time-consuming. We introduce a new methodology, called Lorecast, which accepts English prompts as input to rapidly generate layout-aware performance and power estimates. This approach bypasses the need for HDL code development and synthesis, making it both fast and user-friendly. Experimental results demonstrate that Lorecast achieves accuracy within a few percent of error compared to post-layout analysis, while significantly reducing turnaround time.