LGARApr 16, 2025

Hardware-Friendly Delayed-Feedback Reservoir for Multivariate Time-Series Classification

arXiv:2504.11981v14 citationsh-index: 25IEEE Trans Comput Des Integr Circuit Syst
Originality Incremental advance
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This work addresses the challenge of efficiently implementing reservoir computing for multivariate time-series classification on edge hardware, offering a fully digital solution that reduces circuit size and processing power compared to analog methods.

The authors tackled the problem of converting variable-length features to constant-length intermediate representations in reservoir computing for time-series classification, which typically requires computationally expensive matrix inversion, by proposing a dot-product-based reservoir representation (DPRR) and a hardware-friendly delayed-feedback reservoir (DFR) that achieved superior accuracy and smaller circuit size in FPGA implementations across 12 tasks.

Reservoir computing (RC) is attracting attention as a machine-learning technique for edge computing. In time-series classification tasks, the number of features obtained using a reservoir depends on the length of the input series. Therefore, the features must be converted to a constant-length intermediate representation (IR), such that they can be processed by an output layer. Existing conversion methods involve computationally expensive matrix inversion that significantly increases the circuit size and requires processing power when implemented in hardware. In this article, we propose a simple but effective IR, namely, dot-product-based reservoir representation (DPRR), for RC based on the dot product of data features. Additionally, we propose a hardware-friendly delayed-feedback reservoir (DFR) consisting of a nonlinear element and delayed feedback loop with DPRR. The proposed DFR successfully classified multivariate time series data that has been considered particularly difficult to implement efficiently in hardware. In contrast to conventional DFR models that require analog circuits, the proposed model can be implemented in a fully digital manner suitable for high-level syntheses. A comparison with existing machine-learning methods via field-programmable gate array implementation using 12 multivariate time-series classification tasks confirmed the superior accuracy and small circuit size of the proposed method.

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