Enhancing Reinforcement Learning for the Floorplanning of Analog ICs with Beam Search
This addresses the complex trade-offs in analog IC layout design for circuit engineers, though it appears incremental as it builds on existing RL methods.
The paper tackles the challenge of automating analog IC floorplanning by combining reinforcement learning with beam search, resulting in approximately 5-85% improvements in area, dead space, and wire length compared to standard RL approaches.
The layout of analog ICs requires making complex trade-offs, while addressing device physics and variability of the circuits. This makes full automation with learning-based solutions hard to achieve. However, reinforcement learning (RL) has recently reached significant results, particularly in solving the floorplanning problem. This paper presents a hybrid method that combines RL with a beam (BS) strategy. The BS algorithm enhances the agent's inference process, allowing for the generation of flexible floorplans by accomodating various objective weightings, and addressing congestion without without the need for policy retraining or fine-tuning. Moreover, the RL agent's generalization ability stays intact, along with its efficient handling of circuit features and constraints. Experimental results show approx. 5-85% improvement in area, dead space and half-perimeter wire length compared to a standard RL application, along with higher rewards for the agent. Moreover, performance and efficiency align closely with those of existing state-of-the-art techniques.