GAVINA: flexible aggressive undervolting for bit-serial mixed-precision DNN acceleration
This addresses energy efficiency in DNN acceleration for hardware systems, though it appears incremental as it builds on undervolting and bit-serial methods.
The paper tackled the high error rate and limited precision of undervolting for DNN acceleration by proposing GAVINA, a flexible architecture combining undervolting and bit-serial computation, achieving up to 89 TOP/sW energy efficiency and a 20% boost with negligible accuracy loss on ResNet-18.
Voltage overscaling, or undervolting, is an enticing approximate technique in the context of energy-efficient Deep Neural Network (DNN) acceleration, given the quadratic relationship between power and voltage. Nevertheless, its very high error rate has thwarted its general adoption. Moreover, recent undervolting accelerators rely on 8-bit arithmetic and cannot compete with state-of-the-art low-precision (<8b) architectures. To overcome these issues, we propose a new technique called Guarded Aggressive underVolting (GAV), which combines the ideas of undervolting and bit-serial computation to create a flexible approximation method based on aggressively lowering the supply voltage on a select number of least significant bit combinations. Based on this idea, we implement GAVINA (GAV mIxed-precisioN Accelerator), a novel architecture that supports arbitrary mixed precision and flexible undervolting, with an energy efficiency of up to 89 TOP/sW in its most aggressive configuration. By developing an error model of GAVINA, we show that GAV can achieve an energy efficiency boost of 20% via undervolting, with negligible accuracy degradation on ResNet-18.