Q-StaR: A Quasi-Static Routing Scheme for NoCs
This addresses load balancing issues in networks-on-chip for chip designers, offering significant performance gains but is incremental as it builds on existing routing methods.
The paper tackles the problem of load balancing in networks-on-chip by proposing Q-StaR, a quasi-static routing scheme that improves throughput by 42.9% under uniform traffic and reduces mean and maximum latency by 86.4% and 95.3% under realistic workloads.
In networks-on-chip, static routing schemes are favored for their simplicity and predictability, but they cannot effectively balance network load due to the unawareness of runtime load distribution. Q-StaR discovers two factors (topology and traffic distribution) that determine the long-term trend of load distribution, and proposes N-Rank to extract this trend. The obtained information is used to guide BiDOR's route selection at runtime, thereby improving load balancing while retaining simplicity and predictability. Simulation validates that Q-StaR significantly outperforms the typical dimension-order routing (throughput under uniform traffic improved by 42.9\%, and mean/maximum latency under realistic workloads reduced by 86.4\%/95.3\%).