An FPGA Implementation of Displacement Vector Search for Intra Pattern Copy in JPEG XS
This work addresses hardware deployment challenges for low-latency image compression, but it is incremental as it optimizes an existing module for practical implementation.
The paper tackled the computationally intensive displacement vector search in JPEG XS's Intra Pattern Copy tool by proposing an efficient pipelined FPGA architecture, achieving a throughput of 38.3 Mpixels/s with 277 mW power consumption.
Recently, progress has been made on the Intra Pattern Copy (IPC) tool for JPEG XS, an image compression standard designed for low-latency and low-complexity coding. IPC performs wavelet-domain intra compensation predictions to reduce spatial redundancy in screen content. A key module of IPC is the displacement vector (DV) search, which aims to solve the optimal prediction reference offset. However, the DV search process is computationally intensive, posing challenges for practical hardware deployment. In this paper, we propose an efficient pipelined FPGA architecture design for the DV search module to promote the practical deployment of IPC. Optimized memory organization, which leverages the IPC computational characteristics and data inherent reuse patterns, is further introduced to enhance the performance. Experimental results show that our proposed architecture achieves a throughput of 38.3 Mpixels/s with a power consumption of 277 mW, demonstrating its feasibility for practical hardware implementation in IPC and other predictive coding tools, and providing a promising foundation for ASIC deployment.