Evaluating Four FPGA-accelerated Space Use Cases based on Neural Network Algorithms for On-board Inference
This work addresses the challenge of data downlink pressure in space missions by enabling onboard processing, though it is incremental as it applies existing FPGA tools to specific use cases.
The paper tackled the problem of high data volumes from space sensors exceeding onboard capacity by evaluating FPGA acceleration of neural networks for onboard inference across four space use cases, achieving up to 34.16× higher inference rates and reduced energy per inference compared to CPU baselines.
Space missions increasingly deploy high-fidelity sensors that produce data volumes exceeding onboard buffering and downlink capacity. This work evaluates FPGA acceleration of neural networks (NNs) across four space use cases on the AMD ZCU104 board. We use Vitis AI (AMD DPU) and Vitis HLS to implement inference, quantify throughput and energy, and expose toolchain and architectural constraints relevant to deployment. Vitis AI achieves up to 34.16$\times$ higher inference rate than the embedded ARM CPU baseline, while custom HLS designs reach up to 5.4$\times$ speedup and add support for operators (e.g., sigmoids, 3D layers) absent in the DPU. For these implementations, measured MPSoC inference power spans 1.5-6.75 W, reducing energy per inference versus CPU execution in all use cases. These results show that NN FPGA acceleration can enable onboard filtering, compression, and event detection, easing downlink pressure in future missions.