CoverAssert: Iterative LLM Assertion Generation Driven by Functional Coverage via Syntax-Semantic Representations
This addresses the challenge of improving functional coverage in hardware verification for IC designers, though it is incremental as it builds on existing methods like AssertLLM and Spec2Assertion.
The paper tackled the problem of LLMs generating SystemVerilog assertions with insufficient functional coverage by proposing CoverAssert, an iterative framework that uses coverage feedback to guide LLM generation, resulting in average improvements of 9.57% in branch coverage, 9.64% in statement coverage, and 15.69% in toggle coverage on four open-source designs.
LLMs can generate SystemVerilog assertions (SVAs) from natural language specs, but single-pass outputs often lack functional coverage due to limited IC design understanding. We propose CoverAssert, an iterative framework that clusters semantic and AST-based structural features of assertions, maps them to specifications, and uses functional coverage feedback to guide LLMs in prioritizing uncovered points. Experiments on four open-source designs show that integrating CoverAssert with AssertLLM and Spec2Assertion improves average improvements of 9.57 % in branch coverage, 9.64 % in statement coverage, and 15.69 % in toggle coverage.