Trilinear Compute-in-Memory Architecture for Energy-Efficient Transformer Acceleration
This addresses energy and latency inefficiencies in Transformer accelerators for AI applications, representing a novel architectural advancement rather than an incremental improvement.
The paper tackled the problem of costly non-volatile memory reprogramming in Compute-in-Memory accelerators for Transformers by introducing TrilinearCIM, a Double-Gate FeFET-based architecture that avoids dynamic reprogramming, resulting in up to 46.6% energy reduction and 20.4% latency improvement over conventional FeFET CIM.
Self-attention in Transformers generates dynamic operands that force conventional Compute-in-Memory (CIM) accelerators into costly non-volatile memory (NVM) reprogramming cycles, degrading throughput and stressing device endurance. Existing solutions either reduce but retain NVM writes through matrix decomposition or sparsity, or move attention computation to digital CMOS at the expense of NVM density. We present TrilinearCIM, a Double-Gate FeFET (DG-FeFET)-based architecture that uses back-gate modulation to realize a three-operand multiply-accumulate primitive for in-memory attention computation without dynamic ferroelectric reprogramming. Evaluated on BERT-base (GLUE) and ViT-base (ImageNet and CIFAR), TrilinearCIM outperforms conventional CIM on seven of nine GLUE tasks while achieving up to 46.6\% energy reduction and 20.4\% latency improvement over conventional FeFET CIM at 37.3\% area overhead. To our knowledge, this is the first architecture to perform complete Transformer attention computation exclusively in NVM cores without runtime reprogramming.