31.1 A 14.08-to-135.69Token/s ReRAM-on-Logic Stacked Outlier-Free Large-Language-Model Accelerator with Block-Clustered Weight-Compression and Adaptive Parallel-Speculative-Decoding
For LLM inference acceleration, this work demonstrates a hardware-software co-design that improves throughput and energy efficiency over prior speculative decoding approaches.
This paper presents a ReRAM-on-logic stacked LLM accelerator that achieves 14.08-to-135.69 token/s and 4.46-to-7.17x speedup over vanilla speculative decoding using block-clustered weight compression and adaptive parallel speculative decoding.
This work presents a 55nm speculative decoding-based LLM accelerator with bumping-based face-to-face ReRAM-on-logic stacking technology. It features a local rotation unit for outlier-free low-bit quantization, a stacking-aware PNM architecture co-designed with blockwise vector quantization to reduce weight EMA overheads, and an adaptive parallel speculative decoding scheme with an out-of-order scheduler for high resource and bandwidth utilization. Our chip achieves 14.08-to-135.69token/s and 4.46-to-7.17x speedup over vanilla speculative decoding.