ARMay 23

An Energy-Efficient Approximate Posit Multiply-Divide Unit

arXiv:2605.246656.5
Predicted impact top 92% in AR · last 90 daysOriginality Synthesis-oriented
AI Analysis

For hardware designers of energy-efficient computing systems, this work offers a low-cost approximate division unit for the posit number system, though it is incremental as it applies known approximation techniques to a specific number format.

This paper proposes an approximate division method for the posit number system that uses a look-up table and a single subtraction to compute the reciprocal, achieving a 78.8% reduction in power-delay product and requiring only 46.33% of the area compared to an exact division design.

In modern computing units, division operations are generally slower than other arithmetic operations and require more resources, such as area and power, than multiplication. To reduce the delay, fast division algorithms use an initial approximation of the reciprocal of the divisor and iteratively approach the correct value, followed by multiplication with the dividend. The hardware architecture and choice of algorithm can significantly alter the overall performance of the division unit. This paper proposes a reduced-accuracy division method for the posit number system, which is an alternative to the traditional floating-point system. The proposed design uses a Look-Up Table (LUT) and a single subtraction operation to perform approximate divisor reciprocation by leveragingthemathematicalsymmetriesofthepositnumbersystem.The paper also presents a hardware architecture that combines multiplication and division units. The reciprocal calculation has been incorporated into the posit Decoder, a common unit required to perform any hardware operation with posits. Compared to existing hardware implementations of division, the proposed method requires significantly fewer operations at the cost of perfect rounding for division. The proposed architecture was simulated using the Cadence RTL v7.1 E2 compiler at the TSMC 90 nm process node and achieves a Power Delay Product (PDP) reduction of 78.8% compared to an existing design that performs exact division, while only 46.33% of the area is required. The experimental results also demonstrate the effectiveness of the proposed system in improving the efficiency of multiplication in posit-based systems.

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