ARAISYSYJun 13

LLM4RTL: Tool-Assisted LLM for RTL Generation

arXiv:2606.155008.0
Predicted impact top 35% in AR · last 90 daysOriginality Incremental advance
AI Analysis

For hardware design engineers, this work improves automated RTL code generation by enhancing LLM performance with smaller models, but the approach is incremental and domain-specific.

The paper proposes a JRCRC pipeline to filter and refine RTL code-generation training data, and a tool-assisted architecture to improve LLM reasoning for RTL generation. The system achieves performance comparable to GPT-4O with a much smaller LLM, outperforming many state-of-the-art methods on VerilogEval.

Large language models (LLMs) have facilitated impressive progress in software engineering, code generation, tooling, and systems. Concurrently, a significant body of research has developed which explores a growing variety of methods and systems for applying LLMs to hardware and chip design (e.g., systems for RTL code generation based on functional description). However, when it comes to open Verilog/RTL code-generation, we need high-quality training samples to build specialized and more effective LLM systems through fine-tuning or low-rank adaptation. Here, we propose a ``judge-renew-check-renew-check'' (JRCRC) pipeline which updates a current public dataset using a hierarchy of state-of-the-art commercial LLM models differing in their costs and capabilities in RTL code generation. This approach achieves a cost-effective mechanism for filtering and refining code-generation samples into a higher-quality training dataset. Our experiments also identify some common weaknesses of LLMs in rule-based reasoning and logic, and consequently, in RTL code-generation. Having identified these weaknesses, we develop an architecture for incorporating pre-processing tools to dynamically assist the LLMs in inferring logical relationships from tabular data formats. With our tools-assisted architecture for RTL code generation, we achieve significant overall performance gains in the VerilogEval benchmark and outperform many state-of-the-art methods. Our LLM4RTL system achieves performance comparable to that of GPT-4O using a significantly much smaller LLM.

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