Row-Based Layout Synthesis for Analog Circuits Using Height-Quantized Primitives
It addresses the challenge of analog layout automation in advanced nodes by improving design predictability and reducing performance degradation, but the approach is incremental.
This paper presents a quantized row-height layout synthesis methodology for analog and mixed-signal circuits that reduces the schematic-to-postlayout performance gap by up to 68.5% and achieves up to 24.1% area reduction compared to custom baseline designs.
Restrictive design rules and strong layout-dependent effects have tightened the coupling between physical layout decisions and electrical performance in advanced process nodes, such as FinFET, making analog and mixed-signal (AMS) layout automation increasingly difficult. This paper presents a quantized row-height layout synthesis methodology for AMS circuits, a methodology that has previously been shown to reduce the simulation-to-silicon gap. The proposed flow optimizes a row height fabric from circuit requirements and layout constraints while mapping analog building blocks into quantized-height rows. Results on multiple testcases demonstrate that the proposed flow synthesizes layouts with similar postlayout performance relative to less-constrained custom baseline designs, with comparable performance metrics. Our quantized-height designs are shown to reduce the schematic-to-postlayout performance gap by up to 68.5% and result in lower area for most of our testcases, with a maximum area reduction of 24.1%.