Ramesh Harjani

Subhadip Ghosh, Ramesh Harjani, Sachin S. Sapatnekar

This work presents NEMESIS, a multimodal framework for operational transconductance amplifier (OTA) design using large language models (LLMs). NEMESIS strikes a balance between fast, approximate analytical models vs. accurate, computationally expensive SPICE evaluations. Given an OTA netlist and schematic, NEMESIS first identifies circuit primitives and then generates progressively more accurate performance equations. The framework begins with equations retrieved from the prior invocations of NEMESIS to structurally similar OTAs, if available; otherwise, it uses the LLM to derive the initial equations directly from the circuit input. These equations are iteratively refined via a SPICE-based repair loop. In a commercial 65nm PDK, NEMESIS is demonstrated on five OTA topologies, producing SPICE-verified equations across biasing ranges with <7% average relative error and a post-convergence evaluation speedup of ~4622x over full SPICE-based evaluation.

Endalk Y. Gebru, Ramprasath S., Ramesh Harjani et al.

Restrictive design rules and strong layout-dependent effects have tightened the coupling between physical layout decisions and electrical performance in advanced process nodes, such as FinFET, making analog and mixed-signal (AMS) layout automation increasingly difficult. This paper presents a quantized row-height layout synthesis methodology for AMS circuits, a methodology that has previously been shown to reduce the simulation-to-silicon gap. The proposed flow optimizes a row height fabric from circuit requirements and layout constraints while mapping analog building blocks into quantized-height rows. Results on multiple testcases demonstrate that the proposed flow synthesizes layouts with similar postlayout performance relative to less-constrained custom baseline designs, with comparable performance metrics. Our quantized-height designs are shown to reduce the schematic-to-postlayout performance gap by up to 68.5% and result in lower area for most of our testcases, with a maximum area reduction of 24.1%.

Kishor Kunal, Jitesh Poojary, Tonmoy Dhar et al.

Analog layout synthesis requires some elements in the circuit netlist to be matched and placed symmetrically. However, the set of symmetries is very circuit-specific and a versatile algorithm, applicable to a broad variety of circuits, has been elusive. This paper presents a general methodology for the automated generation of symmetry constraints, and applies these constraints to guide automated layout synthesis. While prior approaches were restricted to identifying simple symmetries, the proposed method operates hierarchically and uses graph-based algorithms to extract multiple axes of symmetry within a circuit. An important ingredient of the algorithm is its ability to identify arrays of repeated structures. In some circuits, the repeated structures are not perfect replicas and can only be found through approximate graph matching. A fast graph neural network based methodology is developed for this purpose, based on evaluating the graph edit distance. The utility of this algorithm is demonstrated on a variety of circuits, including operational amplifiers, data converters, equalizers, and low-noise amplifiers.