DSJun 24

Parameterized Complexity of Power Network Design: Coordinating Cable Placement is Hard

arXiv:2606.258596.5
Predicted impact top 64% in DS · last 90 daysOriginality Incremental advance
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This work provides complexity classifications for power network design problems, which are important for infrastructure planning, but the results are largely negative (hardness) and incremental over known Steiner Tree variants.

The paper studies the parameterized complexity of power network design problems, showing that while Steiner Tree is fixed-parameter tractable, most variants are W[1]-hard when parameterized by the number of terminals. For low-voltage networks, an XP-algorithm for planar inputs is presented, and for high-voltage networks, W[1]-hardness holds even on planar graphs.

We study generalizations of the Steiner Tree problem motivated by the design of power networks. While Steiner Tree asks for a single minimum-cost tree connecting given terminal vertices, a power network typically consists of multiple trees, each connecting a subset of the terminals, to avoid electrical overloads. The cost of installing depends on both the cable lengths and the cost of digging underground trenches for putting the cables where the digging costs can be shared. These leads to variants of Steiner Tree where the goal is to compute a minimum-cost set of Steiner trees with a common root, that together connect all terminals while balancing the power demand of the terminals in each tree. Two important variants arise depending on whether the network is intended for low-voltage or high-voltage power. In the low-voltage case, power loss imposes a bound on the maximum depth of each tree, while no such restriction applies in the high-voltage case. We study the parameterized complexity of several power network design problems, parameterized by the number of terminals. While Steiner Tree is fixed-parameter tractable under this parameterization, most of our variants are W[1]-hard. For low-voltage networks, we present an XP-algorithm for planar inputs based on structural bounds on the treewidth of solution subgraphs. We also give a reduction from Grid Tiling showing tightness under ETH. The XP-algorithm extends to the high-voltage setting and general graphs, albeit at a cost in the running time. For high-voltage networks, we show the problem remains W[1]-hard even on planar graphs. Finally, we explore a variant of the cost model for sharing digging costs in which both problems become fixed-parameter tractable.

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