Xiaolin He

Xiaolin He, Zirui Li, Xinwei Wang et al.

Perceived risk in automated driving is often measured as discrete scores that summarise riding experience but this obscures volatile peaks from sustained elevation. Here we treat discrete clipwise ratings as constraints on an unobserved inferred evolution and apply a kernel constrained inverse model to infer the temporal evolution of perceived risk. Across 2,164 participants and 141,628 discrete clipwise ratings spanning 236 hours of scripted motorway interactions, we infer evolutions under kernel constraints whose shapes follow priors from independent handset-based ratings and whose timing is fixed by scripted manoeuvre markers. The inferred perceived risk evolutions differentiate accumulated perceived risk from within clip concentration, revealing scenario differences that are not identifiable from peak judgements alone. We then map these inferred evolutions from observable vehicle and relative motion cues under strict event level holdout using a deep neural network, enabling interpretable attribution analyses. Attribution shows distinct patterns between risk rising and falling segments, with a shift toward conflict cues in the rising phase, and a rebound toward stability cues in the falling phase. Attribution concentration increases only modestly at high perceived risk levels. These results move beyond treating perceived risk as a single severity score by characterising within episode dynamics and phase dependent cue associations in scripted motorway interactions.

Cenlin Duan, Jianlei Yang, Xiaolin He et al.

Processing-in-memory (PIM), as a novel computing paradigm, provides significant performance benefits from the aspect of effective data movement reduction. SRAM-based PIM has been demonstrated as one of the most promising candidates due to its endurance and compatibility. However, the integration density of SRAM-based PIM is much lower than other non-volatile memory-based ones, due to its inherent 6T structure for storing a single bit. Within comparable area constraints, SRAM-based PIM exhibits notably lower capacity. Thus, aiming to unleash its capacity potential, we propose DDC-PIM, an efficient algorithm/architecture co-design methodology that effectively doubles the equivalent data capacity. At the algorithmic level, we propose a filter-wise complementary correlation (FCC) algorithm to obtain a bitwise complementary pair. At the architecture level, we exploit the intrinsic cross-coupled structure of 6T SRAM to store the bitwise complementary pair in their complementary states ($Q/\overline{Q}$), thereby maximizing the data capacity of each SRAM cell. The dual-broadcast input structure and reconfigurable unit support both depthwise and pointwise convolution, adhering to the requirements of various neural networks. Evaluation results show that DDC-PIM yields about $2.84\times$ speedup on MobileNetV2 and $2.69\times$ on EfficientNet-B0 with negligible accuracy loss compared with PIM baseline implementation. Compared with state-of-the-art SRAM-based PIM macros, DDC-PIM achieves up to $8.41\times$ and $2.75\times$ improvement in weight density and area efficiency, respectively.

Yingjie Qi, Jianlei Yang, Yiou Wang et al.

Digital Compute-in-Memory (CIM) architectures have shown great promise in Deep Neural Network (DNN) acceleration by effectively addressing the "memory wall" bottleneck. However, the development and optimization of digital CIM accelerators are hindered by the lack of comprehensive tools that encompass both software and hardware design spaces. Moreover, existing design and evaluation frameworks often lack support for the capacity constraints inherent in digital CIM architectures. In this paper, we present CIMFlow, an integrated framework that provides an out-of-the-box workflow for implementing and evaluating DNN workloads on digital CIM architectures. CIMFlow bridges the compilation and simulation infrastructures with a flexible instruction set architecture (ISA) design, and addresses the constraints of digital CIM through advanced partitioning and parallelism strategies in the compilation flow. Our evaluation demonstrates that CIMFlow enables systematic prototyping and optimization of digital CIM architectures across diverse configurations, providing researchers and designers with an accessible platform for extensive design space exploration.