Enabling Resource-Aware Mapping of Spiking Neural Networks via Spatial Decomposition
This work addresses a resource-mapping problem for SNN applications on neuromorphic hardware, offering a novel solution that improves efficiency and model quality, though it is incremental as it builds on an existing mapping framework.
The paper tackles the challenge of mapping complex Spiking Neural Networks (SNNs) onto neuromorphic hardware without pruning connections, which typically causes accuracy loss, by proposing a spatial decomposition technique that unrolls neurons into homogeneous units with two pre-synaptic connections. This approach results in a 60% lower crossbar requirement, 9x higher synapse utilization, 62% lower wasted energy, and up to a 4.6% increase in model quality on DYNAP-SE hardware.
With growing model complexity, mapping Spiking Neural Network (SNN)-based applications to tile-based neuromorphic hardware is becoming increasingly challenging. This is because the synaptic storage resources on a tile, viz. a crossbar, can accommodate only a fixed number of pre-synaptic connections per post-synaptic neuron. For complex SNN models that have many pre-synaptic connections per neuron, some connections may need to be pruned after training to fit onto the tile resources, leading to a loss in model quality, e.g., accuracy. In this work, we propose a novel unrolling technique that decomposes a neuron function with many pre-synaptic connections into a sequence of homogeneous neural units, where each neural unit is a function computation node, with two pre-synaptic connections. This spatial decomposition technique significantly improves crossbar utilization and retains all pre-synaptic connections, resulting in no loss of the model quality derived from connection pruning. We integrate the proposed technique within an existing SNN mapping framework and evaluate it using machine learning applications on the DYNAP-SE state-of-the-art neuromorphic hardware. Our results demonstrate an average 60% lower crossbar requirement, 9x higher synapse utilization, 62% lower wasted energy on the hardware, and between 0.8% and 4.6% increase in model quality.