NEARETAug 4, 2021

DFSynthesizer: Dataflow-based Synthesis of Spiking Neural Networks to Neuromorphic Hardware

arXiv:2108.02023v137 citations
Originality Incremental advance
AI Analysis

This work addresses a domain-specific problem for researchers and engineers deploying SNN-based machine learning on neuromorphic hardware, offering an incremental improvement in synthesis methods.

The authors tackled the challenge of synthesizing Spiking Neural Network (SNN) programs to neuromorphic hardware, which is difficult due to resource and latency limitations, and proposed DFSynthesizer, an end-to-end framework that uses dataflow analysis and scheduling to guarantee hardware performance, demonstrating much tighter performance guarantees compared to current mapping approaches in evaluations with 10 machine-learning programs.

Spiking Neural Networks (SNN) are an emerging computation model, which uses event-driven activation and bio-inspired learning algorithms. SNN-based machine-learning programs are typically executed on tile- based neuromorphic hardware platforms, where each tile consists of a computation unit called crossbar, which maps neurons and synapses of the program. However, synthesizing such programs on an off-the-shelf neuromorphic hardware is challenging. This is because of the inherent resource and latency limitations of the hardware, which impact both model performance, e.g., accuracy, and hardware performance, e.g., throughput. We propose DFSynthesizer, an end-to-end framework for synthesizing SNN-based machine learning programs to neuromorphic hardware. The proposed framework works in four steps. First, it analyzes a machine-learning program and generates SNN workload using representative data. Second, it partitions the SNN workload and generates clusters that fit on crossbars of the target neuromorphic hardware. Third, it exploits the rich semantics of Synchronous Dataflow Graph (SDFG) to represent a clustered SNN program, allowing for performance analysis in terms of key hardware constraints such as number of crossbars, dimension of each crossbar, buffer space on tiles, and tile communication bandwidth. Finally, it uses a novel scheduling algorithm to execute clusters on crossbars of the hardware, guaranteeing hardware performance. We evaluate DFSynthesizer with 10 commonly used machine-learning programs. Our results demonstrate that DFSynthesizer provides much tighter performance guarantee compared to current mapping approaches.

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