ParaGate: Parasitic-Driven Domain Adaptation Transfer Learning for Netlist Performance Prediction
This addresses a domain-specific problem for electronic design automation (EDA) engineers by enabling earlier optimization, though it is incremental as it builds on existing neural-network-based solutions.
The paper tackles the problem of predicting layout-level timing and power from netlists in EDA flows, where traditional methods are hindered by late-stage availability and generalization issues, achieving strong generalization with minimal fine-tuning data, such as improving arrival-time R2 from 0.119 to 0.897 on openE906.
In traditional EDA flows, layout-level performance metrics are only obtainable after placement and routing, hindering global optimization at earlier stages. Although some neural-network-based solutions predict layout-level performance directly from netlists, they often face generalization challenges due to the black-box heuristics of commercial placement-and-routing tools, which create disparate data across designs. To this end, we propose ParaGate, a three-step cross-stage prediction framework that infers layout-level timing and power from netlists. First, we propose a two-phase transfer-learning approach to predict parasitic parameters, pre-training on mid-scale circuits and fine-tuning on larger ones to capture extreme conditions. Next, we rely on EDA tools for timing analysis, offloading the long-path numerical reasoning. Finally, ParaGate performs global calibration using subgraph features. Experiments show that ParaGate achieves strong generalization with minimal fine-tuning data: on openE906, its arrival-time R2 from 0.119 to 0.897. These results demonstrate that ParaGate could provide guidance for global optimization in the synthesis and placement stages.