Lightweight True In-Pixel Encryption with FeFET Enabled Pixel Design for Secure Imaging
This provides hardware-level protection for secure imaging against neural-network-based inference, though it is incremental as it builds on existing encryption and pixel design concepts.
The paper tackles the problem of securing image sensors by introducing a compact pixel architecture that performs true in-pixel encryption using a ferroelectric field-effect transistor, resulting in a pixel pitch of 2.33 x 3.01 um² and reducing ResNet-18 recognition accuracy from 99.29% to 9.58% on MNIST and from 91.33% to 6.98% on CIFAR-10 after encryption.
Ensuring end-to-end security in image sensors has become essential as visual data can be exposed through multiple stages of the imaging pipeline. Advanced protection requires encryption to occur before pixel values appear on any readout lines. This work introduces a secure pixel sensor (SecurePix), a compact CMOS-compatible pixel architecture that performs true in-pixel encryption using a symmetric key realized through programmable, non-volatile multidomain polarization states of a ferroelectric field-effect transistor. The pixel and array operations are designed and simulated in HSPICE, while a 45 nm CMOS process design kit is used for layout drawing. The resulting layout confirms a pixel pitch of 2.33 x 3.01 um^2. Each pixel's non-volatile programming level defines its analog transfer characteristic, enabling the photodiode voltage to be converted into an encrypted analog output within the pixel. Full-image evaluation shows that ResNet-18 recognition accuracy drops from 99.29 percent to 9.58 percent on MNIST and from 91.33 percent to 6.98 percent on CIFAR-10 after encryption, indicating strong resistance to neural-network-based inference. Lookup-table-based inverse mapping enables recovery for authorized receivers using the same symmetric key. Based on HSPICE simulation, the SecurePix achieves a per-pixel programming power-delay product of 17 uW us and a per-pixel sensing power-delay product of 1.25 uW us, demonstrating low-overhead hardware-level protection.