FlowPlace: Flow Matching for Chip Placement
For chip design automation, FlowPlace addresses key limitations of generative placement models (slow sampling, overlaps, poor pre-training) with a practical solution.
FlowPlace introduces a flow-matching generative model for chip placement that achieves better PPA metrics, 10-50× faster sampling, and zero overlaps compared to prior diffusion-based methods.
Chip placement plays an important role in physical design. While generative models like diffusion models offer promising learning-based solutions, current methods have the following limitations: they use random synthetic data for pre-training, require long sampling times, and often result in overlaps due to their dependence on gradient-based solvers during the sampling process. To overcome these issues, we propose FlowPlace, which features mask-guided synthetic data generation, flow-based efficient training with flexible prior injection, and hard constraint sampling for overlap-free layouts. Experiments on OpenROAD and ICCAD 2015 benchmarks show FlowPlace achieves better PPA metrics, 10-50$\times$ faster sampling efficiency, and zero overlaps.